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| NJU8721 PRELIMINARY CLASS D HEADPHONE AMPLIFIER FOR DIGITAL AUDIO ! GENERAL DESCRIPTION The NJU8721 is a class D Headphone Amplifier th featuring 6 modulation. It includes Digital Attenuator, Mute, and De-emphasis circuits. It converts Digital source input to PWM signal output which is output PWM signal converted to analog signal with simple external LC Filter. The NJU8721 realizes very high power-efficiency by class D operation. Therefore, it is suitable for portable audio set and others. ! PACKAGE OUTLINE NJU8721V ! FEATURES # Stereo Headphone Power Amplifier : 50mW+50mW # Sixth-order 32fS Over Sampling & PWM # Internal 8fS Over Sampling Digital Filter # Sampling Frequency : 96kHz (Max.) # De-Emphasis : 32kHz, 44.1kHz, 48kHz # System Clock : 256fS # Digital Processing : Attenuator 107step, LOG Curve : Mute # Digital Audio Interface : 16bit, 18bit 2 : I S, LSB Justified, MSB Justified # Operating Voltage : 3.0 to 3.6V # Driving Voltage : VDD to 5.25V # C-MOS Technology # Package Outline : SSOP20 ! PIN CONFIGURATION STBY TEST VSSR OUTR VDDR VDDL OUTL VSSL MODE RST 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD F0/DATA F1/REQ F2/SCK MUTE DIN LRCK BCK MCK VSS ! BLOCK DIAGRAM VDD VSS RST MCK LRCK BCK DIN MUTE STBY MODE F0/DATA F1/REQ F2/SCK Power On Reset Circuit VDDL Synchronization Circuit Serial Audio Data Interface 8fS Over Sampling Digital Filter 32fS 6 & PWM th OUTL VSSL VDDR OUTR System Control VSSR -1- NJU8721 ! TERMINAL DESCRIPTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL STBY TEST VSSR OUTR VDDR VDDL OUTL VSSL MODE RST VSS MCK BCK LRCK DIN MUTE F2/SCK F1/REQ F0/DATA VDD I/O I I - O - - O - I I - I I I I I I I I - FUNCTION Standby Control Terminal Low : Standby ON High : Standby OFF Manufacturer Testing Terminal Normally connect to GND. Rch Power GND, VSSR=0V Rch Output Terminal Rch Power Supply, VDDR=VDD to 5.0V Lch Power Supply, VDDL=VDD to 5.0V Lch Output terminal Lch Power GND, VSSL=0V Control Mode selection Terminal Low : Parallel Control Mode High : Serial Control Mode Reset Terminal Low : Reset ON High : Reset OFF Logic Power GND, VSS=0V Master Clock Input Terminal 256fS clock inputs this terminal. Serial Audio Data Bit Clock Input Terminal This clock must synchronize with MCK input signal. L/R Channel Clock Input Terminal This clock must synchronize with MCK input signal. Serial Audio Data Input Terminal Mute Control Terminal Low : Mute ON High : Mute OFF MODE="Low" : Serial Audio Interface Format Selection Terminal 2 MODE="High" : Control Register Data Shift Clock Input Terminal The data is fetched into the control register by rise edge of SCK signal. MODE="Low" : Serial Audio Interface Format Selection Terminal 1 MODE="High" : Control Register Data Request Input Terminal MODE="Low" : Serial Audio Interface Format Selection Terminal 0 MODE="High" : Control Register Data Input Terminal Logic Power Supply, VDD=3.3V ! INPUT TERMINAL STRUCTURE VDD Input Terminal VSS Inside Circuit -2- NJU8721 ! FUNCTIONAL DESCRIPTION (1) Signal Output PWM signals of L channel and R output from OUTL and OUTR terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching regulator because Output THD is effected by power supply stability. (2) Master Clock Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock. (3) Reset "L" level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset signal. This Reset signal initializes the internal function setting registers also. During initialization, the output-drivers output GND level. The reset equivalent circuit is shown bellow. RST Power on Reset CLK (About 10kHz) Internal Reset D D D D D D D D Figure 1. Reset Equivalent Circuit (4) 8fS Over Sampling Digital Filter 8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise. It realizes Attenuation and De-Emphasis function by serial function control. (5) 32fS 6 & PWM th 32fS 6 & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM data. th -3- NJU8721 (6) System Control (6-1) Standby Standby functions by "L" level input to the STBY terminal. In busy of Standby, conditions of digital audio format set, attenuation level, de-emphasis, and attenuator operation time are kept and output terminals of OUTL and OUTR are high-impedance. (6-2) Control Mode Set A control mode as shown below is selected by the MODE terminal. MODE 0 1 Parallel Serial Control Method Parallel Serial Function Digital Audio interface Format Set Control Register serial data input Terminals F0, F1, F2 DATA, REQ, SCK : Digital Audio Interface Format is set directly by using F0, F1, and F2 terminals. : NJU8721 is controlled serial input data by 3-wire serial interface using DATA, REQ, and SCK terminals By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed. Refer to (8-5)F0,F1,F2 about function of F0, F1, and F2 terminals. Refer to (8)Control Register about function of DATA, REQ, and SCK terminals. (6-3) Mute Mute functions by "L" signal into the MUTE terminal. In busy of mute, a current attenuation value becomes - by internal digital attenuator. And MUTE is stopped by "H" signal into the MUTE terminal, the attenuation value returns from - to previous value. MUTE 0 1 Attenuation Level - Set Value MUTE MCK Attenuation Value Set Value - Figure 2. Mute Timing - 1024/fS 1024/fS Set Value -4- NJU8721 (7) Serial Audio Data Interface (7-1) Input Data Format Selection 2 The digital audio interface format is selected out of I S, MSB Justified or LSB Justified, and 16 bits or 18 bits data length. (7-2) Input Timing Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as shown below: Data Format 2 IS MSB Justified LSB Justified Rising Edge Lch Input Register Rch Input Register Rch Input Register Falling Edge Rch Input Register Lch Input Register Lch Input Register BCK and LRCK must be synchronized with MCK. LRCK BCK DIN Left Channel Right Channel 15 14 13 1 0 2 15 14 13 1 0 Figure 3.1. 16 bits I S Data Format Right Channel LRCK BCK DIN 15 14 13 10 15 14 13 1 0 15 Left Channel Figure 3.2. 16 bits MSB Justified Data Format LRCK BCK DIN 0 Right Channel Left Channel 15 14 3 2 1 0 15 14 3 2 1 0 Figure 3.3. 16 bits LSB Justified Data Format -5- NJU8721 Left Channel LRCK BCK DIN Right Channel 17 16 15 1 0 2 17 16 15 1 0 Figure 3.4. 18 bits I S Data Format Right Channel LRCK BCK DIN 17 16 15 1 0 17 16 15 1 0 17 Left Channel Figure 3.5. 18 bits MSB Justified Data Format LRCK BCK DIN 0 Right Channel Left Channel 17 16 32 1 0 17 16 32 10 Figure 3.6. 18 bits LSB Justified Data Format (7-3) Failure of Synchronization Operation If the MCK clock fluctuates over than 10 clocks against the LRCK and failure of synchronization is detected the attenuation value is set to -. When the LRCK synchronizes with MCK again, the attenuation value returns from - to previous level. Internal Condition Attenuation Value Normal Operation Set Value - Out of Sync. Normal Operation Set Value 1024/fS Figure 4. Out of Synchronization Operation -6- NJU8721 (8) Control Register When Control Mode is set to Serial control by the Mode terminal, the control register sets various modes. The Control Data is fetched by the rising edge of F2/SCK and is set into the control register by the rising edge of F1/REQ. The latest 8 bits data are valid before the F1/REQ rising pulse. F1/REQ F2/SCK F0/DATA B7 B6 B5 B4 B3 B2 B1 B0 Figure 5. Control Register Timing (8-1) Serial Data Format B7 B6 B5 B4 0 ATTN6 ATTN5 ATTN4 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Do not set other data excepting this table. B3 ATTN3 0 F2 0 0 0 0 0 B2 ATTN2 0 F1 0 0 0 MUTT2 0 B1 ATTN1 DEMP1 F0 0 0 0 MUTT1 0 B0 ATTN0 DEMP0 MUTE RST TEST 0 MUTT0 TRST (8-2) ATTN6 to ATTN0 When B7 is "0", B0 to B6 set the attenuation data. When attenuation data is set, the attenuation value is changed to the target value in the period of transition time set by MUTT0 to MUTT2. The attenuation value (ATT) is fixed by following formula. When ATT is 14h or less, the attenuator is set - at reset. (When Control Mode is Parallel Control, ATT is fixed 0db.) ATT=DATA -121[dB] 7Fh=6dB 7Eh=5dB 7Dh=4dB : 79h=0dB : 16h=-99dB 15h=-100dB 14h=- 13h=- : 00h=- (initial value) DATA : attenuation point -7- NJU8721 (8-3) DEMP0, DEMP1 DEMP0 and DEMP1 control De-Emphasis on/off and sampling frequency. DEMP1 DEMP0 De-Emphasis Initial Value ! 0 0 OFF 0 1 32kHz 1 0 44.1kHz 1 1 48kHz (8-4) MUTE Mute operation is controlled by the "MUTE" as same as the MUTE terminal control. MUTE Mute Operation Initial Value ! 0 OFF 1 ON (8-5) F0, F1, F2 F0, F1, and F2 select Digital Audio Interface Format. As same as the F0/DATA, F1/REQ, and F2/SCK terminal control. F0 F1 F2 Interface Format Bit Length Initial Value 2 ! 0 0 0 IS 16 0 0 1 MSB Justified 16 0 1 0 LSB Justified 16 2 1 0 0 IS 18 1 0 1 MSB Justified 18 1 1 0 LSB Justified 18 (8-6) RST When the RST is "1", the control register and inner data (Digital filter, PWM modulator) are initialized. RST Reset Operation Initial Value ! 0 OFF 1 ON (8-7) TRST When the TRST is "1", only inner data (Digital filter, PWM modulator) is initialized. TRST Data Bus Initialize Initial Value ! 0 OFF 1 ON (8-8) MUTT2 to MUTT0 MUTT2 to MUTT0 set the attenuator transition time. This transition time is one attenuation step change time. MUTT2 MUTT1 MUTT0 Operation Time Initial Value ! 0 0 0 1 / fS 0 0 1 2 / fS 0 1 0 4 / fS 0 1 1 8 / fS 1 0 0 16 / fS 1 0 1 32 / fS 1 1 0 64 / fS 1 1 1 128 / fS -8- NJU8721 ! ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation SSOP20 Note 1) Note 2) SYMBOL VDD VDDL VDDR Vin Topr Tstg PD RATING -0.3 to +4.0 -0.5 to +5.5 -0.5 to +5.5 -0.3 to VDD+0.3 -40 to +85 -40 to +125 300 UNIT V V V V C C mW All voltage values are specified as VSS= VSSR= VSSL=0V. If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note 3) Decoupling capacitors should be connected between VDD-VSS, VDDR-VSSR and VDDL-VSSL due to the stabilized operation. ! ELECTRICAL CHARACTERISTICS (Ta=25C, VDD=VDDL=VDDR=3.3V, fS=44.1kHz, Input Signal=1kHz, Input Signal Level at Full Scale Output, MCK=256fS, Load Impedance=16, nd Measuring Band=20Hz to 20kHz, 2 -order 34kHz LC Filter (Q=0.75), unless otherwise noted) SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Note VDD 5.25 V 3.0 3.3 3.6 V Eeff Vo= 0dB 80 % 4 THD16 Po=3mW,RL=16 0.1 % Po16 Vo= 0dB,RL=16 22 48 mW/ch Po08 Vo= 0dB,RL=8 40 80 mW/ch SN A weight 85 90 dB Drange A weight 85 90 dB Echn EIAJ(1kHz) 60 dB CHD MAT PR IST IDD VIH VIL ILK 20Hz to 20kHz Stopping MCK, BCK, LRCK, DIN No-load operating No signal inputted 90 0.7VDD 0 9 3 1 10 14 VDD 0.3VDD 1.0 x 100 dB dB dB A mA V V A 5 PARAMETER VDDL, VDDR Supply Voltage VDD Supply Voltage Output Power Efficiency Output THD Output Power S/N Dynamic Range Channel Separation Output Level Difference Between Lch and Rch Maximum Mute Attenuation Passband Response Power Supply Current At Standby Power Supply Current At Operating Input Voltage Input Leakage Current Note 4) Power Efficiency (%) = OUTL Output Power + OUTR Output Power (W) VDDL Supply Power + VDDR Supply Power (W) Note 5) When the cut-off frequency is 10Hz or less using external AC-coupling capacitor. -9- NJU8721 Note 6) Analog AC Characteristics Test System Analog AC characteristics test system is shown in Figure 6. The analog AC characteristics of NJU8721 nd is measured with 2 -order LC LPF on the test board and Filters in the Audio Analyzer. Digital Data Digital Audio Interface Receiver Chip NJU8721 2 -order LC LPF nd Filters THD Measuring Apparatus NJU8721 Evaluation Board Audio Analyzer Figure 6. Analog AC Characteristics Measurement System 2 -order LPF Filters nd : fc=34kHz, refer to the LPF on Application Circuit. th : 22Hz HPF + 20kHz 10 -order LPF (with the A-Weighting Filter at measuring S/N and Dynamic-range) - 10 - NJU8721 ! TIMING CHARACTERISTICS * Master Clock Input MCK tMCKH tMCKL (Ta=25C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER MCK Frequency MCK Pulse Width (H) MCK Pulse Width (L) Note 7) * SYMBOL fMCKI tMCKH tMCKL CONDITIONS 256fS MIN. 7.28 12 12 TYP. - MAX. 27.648 - UNIT MHz ns ns tMCKI shows the cycle of the MCK signal. Reset Input tRST RST (Ta=25C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER Reset Low Level Width SYMBOL tRST CONDITIONS MIN. 3 tBCLK TYP. - MAX. - UNIT ms * Digital Audio Signal Interface BCK tBLR LRCK tDS DIN tLRB tBCKL tBCKH tDH PARAMETER Audio DAC Sampling Rate DIN Setup Time DIN Hold Time BCK Period BCK Pulse Width (H) BCK Pulse Width (L) LRCK Hold Time LRCK Setup Time SYMBOL fS tDS tDH tBCLK tBCKH tBCKL tBLR tLRB (Ta=25C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT 28 100 KHz 20 ns 20 ns 1/(128fS) ns 20 ns 20 ns 20 ns 20 ns - 11 - NJU8721 * Control Register Interface tRQS tRQH tREH F1/REQ tSCH F2/SCK tSCK B7 B6 tDAS tDAH PARAMETER F2/SCK Period F2/SCK Pulse Width (H) F2/SCK Pulse Width (L) F0/DATA Setup Time F0/DATA Hold Time F1/REQ Pulse Width (H) F2/SCK Setup Time F1/REQ Hold Time SYMBOL tSCK tSCH tSCL tDAS tDAH tREH tRQS tRQH (Ta=25C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT 2 s 0.8 0.8 0.8 0.8 1.6 0.8 0.8 s s s s s s s B5 B4 B3 B2 B1 B0 tSCL * Input Signal Rise and Fall Time tUP tDN (Ta=25C, VDD=VDDL=VDDR=3.3V, unless otherwise noted) PARAMETER Rise Time Fall Time Note 8) SYMBOL tUP tDN CONDITIONS MIN. - TYP. - MAX. 100 100 UNIT ns ns All timings are based on 30% and 70% voltage level of VDD. - 12 - NJU8721 ! APPLICATION CIRCUIT *A915BY-101M is manufactured by TOKO, INC. For further information, please refer to its technical papers. 0.1uF 3.3V 10uF 20 11 VDD VSS MCK BCK LRCK DIN MODE F0/DATA F1/REQ F2/SCK RST STBY MUTE 220uF A915BY-101M 1k 100uH 0.22uF OUTR 4 NJU8721 Mode Control 9 19 18 17 10 1 16 2 VDDR VSSR VDDL VSSL 5 3 6 8 2.2uF 2.2uF 100uF Switching Regulator TEST 2.2uF Note 9) De-coupling capacitors must be connected between each power supply pin and GND pin. Note 10) The power supply for VDDL and VDDR require fast driving response performance such as a switching regulator for THD. Note 11) The bigger capacitor value of AC-coupling capacitors for headphone outputs realize better frequency response characteristics, especially low frequency area. Note 12) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. 1k 100uH 0.22uF Digital Audio Data 12 13 14 15 220uF A915BY-101M OUTL 7 Headphone 16 - 13 - |
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